As integrated circuit devices become faster and more complex, the interconnections between such devices with one another and with other components on a circuit board can limit the performance achievable in an integrated circuit system. Whereas integrated circuit devices, also referred to as "chips", once were mounted into individual packages having arrays of metal pins that interconnected with the metal traces on a circuit board, and with bond wires connecting the chips to the package pins, more advanced designs often must rely on integrated circuit devices that are directly mounted onto the surface of the metal traces of an advanced package or circuit board to ensure adequate interconnect performance.
One example of such an integrated circuit device is known as a "flip chip", which includes a number of solder bumps disposed on one side of the chip that are used to interconnect with corresponding pads on a package, a circuit board, or a multi-chip module (MCM), etc. The flip chip is so named because the flip chip is placed on the package, board, or MCM face down with the solder bumps resting on the corresponding pads on the package, board or MCM. Then, through any number of available surface mount technology (SMT) processes, each of which usually includes the application of heat and/or pressure to the back side of the flip chip, the solder bumps are physically and electrically connected to the pads to securely mount the flip chip. The elimination of bond wires in a flip chip package, or of the entire packaging for a flip chip when directly mounted to a board or MCM, reduces the amount of space on the circuit board occupied by the flip chip, thus permitting more components to be placed on a given size of circuit board. More importantly, however, the total lengths of the interconnections between active device components can be minimized to reduce signal propagation delays and signal distortion and increase the permissible operating speed of the components on the circuit board.
Signals are often routed in an integrated circuit device and on a circuit board using signal traces, which are essentially conductive "wires" manufactured on a device or board. One significant limitation on system performance is known as crosstalk, which occurs when two signals traces are routed proximate one another and a signal present on one trace interferes with and generates noise on the other trace due to electromagnetic coupling (including capacitive coupling) between the traces. Moreover, electromagnetic coupling also results in the presence of a coupling impedance between adjacent traces to skew the signals present on the traces and introduce delays in the signals. Due to both effects, the speed in which a circuit can operate error-free is limited, and thus, the effects directly impact the overall speed and performance of a system.
Also, the adverse effects of both crosstalk and coupling impedance increase as the distance between signal traces decreases. However, as systems become more complex and powerful and require greater functionality, signal traces often must be placed as close together as possible to conserve as much space as possible. Crosstalk and coupling impedance thus become more and more problematic for more advanced designs.
One specific area in which it is particularly desirable to minimize crosstalk and coupling impedance is in the redistribution layer of an integrated circuit device such as a flip chip. A redistribution layer often is used to interconnect the operational circuitry of a device with an array of pads that are used to interconnect a device with a package, MCM or circuit board (e.g., using solder bumps disposed on the pads). The layout of pads in the redistribution layer directly impacts the die size, and consequently, the overall cost of the device. Furthermore, as circuits become more complex, a greater number of interconnects are usually required, so it is desirable to reduce the distance between the pads to increase the circuit density of the pads and thereby permit a larger number of pads to fit within a given area.
Design of an integrated circuit device typically follows a series of design rules, which specify a number of parameters that must be complied with to ensure reliable manufacture and operation. Among other parameters, often minimum trace widths and spacings are defined, which are dependent upon the particular manufacturing process used. However, with conventional redistribution layer designs, the capacitive coupling between adjacent traces often necessitate that traces be spaced and configured with dimensions that are well above the minimums specified by the design rules. As a result, significant space that could otherwise be utilized by a particular manufacturing process is often wasted due to impedance and crosstalk concerns, and circuit density is consequently diminished.
Therefore, a significant need exists for a manner of increasing the density of an integrated circuit device redistribution layer while minimizing coupling impedances and crosstalk within the layer.